Paper Review Records
All Paper Review Records
17 valid samples · Newest publication first
Review days = acceptance date − received date. PDF, DOI, and publisher-page sources are retained.
322
days
Modified compact modeling of tunnel diodes and its applications in ternary logic circuits
AuthorsJingyi Liu; Guangchao Zhao; Philippe Coquet; Mingqiang Huang; Xingli Wang; Beng Kang Tay
AffiliationsCentre for Micro-&Nano-Electronics, School of Electrical and Electronic Engineering, Nanyang Technological University, 639798, Singapore; CNRS International-NTU-Thales Research Alliance (CINTRA) / IRL 3288, Nanyang Technological University, 637553, Singapore; Institut d'Electronique, de Microélectronique et de Nanotechnologie (IEMN), CNRS UMR 8520—Université de Lille, France; School of Artificial Intelligence, Wuhan University, 430072, PR China
323
days
Design of temperature resistant dual band VCO with integrated TFC circuit for studying aging affect using machine learning framework
AuthorsSusankar Borgohain; Khrishtina Dutta; Rashmi Choudhury; Ruchira Mazumdar; Niranjan Jyoti Borah; Pranab Kishore Dutta; Mriganka Gogoi
AffiliationsDepartment of Electronics and Telecommunication Engineering, Assam Engineering College, India; North Eastern Regional Institute of Science and Technology, Assam Don Bosco University, India
309
days
Ultra-low power electronics with steep sub-threshold swing devices, ferroelectric materials, and cryogenic operation
AuthorsDarsen D. Lu; Hao-Yu Lu; Chia-Chi Hsieh; Ting-Yin Huang; Sourav De; Yao-Jen Lee; Kuo-Hsing Kao; Meng-Hsueh Chiang; Yeong-Her Wang
AffiliationsDepartment of Electrical Engineering, National Cheng Kung University, Tainan City, Taiwan; Miin Wu School of Computing, National Cheng Kung University, Tainan City, Taiwan; College of Semiconductor Research, National Tsing Hua University, Hsinchu, Taiwan; Inst. of Pioneer Semiconductor Innovation, National Yang Ming Chiao Tung Univ., Hsinchu, Taiwan
54
days
Pt redistribution in Ni(Pt)Si layers obtained via total vs. partial reactions and its impact on specific contact resistivity
AuthorsSophie Guillemin; Lillà Ferreint-Roselli; Patrice Gergaud; Nicolas Bernier; Isabelle Tinti; Cédric Bomme; Nicolas Gauthier; Philippe Rodriguez
AffiliationsUniv. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France
196
days
Logic and SRAM design co-optimization for A7 monolithic CFETs using backside gate contact-enabled hybrid power delivery
AuthorsHao He; Lijun Xu; Xiaoning Ma; Kunlong An; Yuntian Jia; Yajia Zhang; Zhiqiang Li; Jianyun Liu; He Cao; Zhenhua Wu; Qinzhi Xu
AffiliationsState Key Lab of Fabrication Technologies for Integrated Circuits, EDA Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China; School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing, 100049, China; School of Physics, Zhejiang University, Hangzhou, 310000, China
50
days
High-robustness and high-density VCMA-MRAM with energy-efficient BL-write scheme
AuthorsYaling Wang; Chao Wang; Jiaxin Li; Xiaoyang Xu; Hanbin Wang; Mingche Li; Weimeng Zhao; Zhongzhen Tong; Bi Wang; Zhaohao Wang
AffiliationsSchool of Integrated Circuit Science and Engineering, Beihang University, China; Hangzhou International Innovation Institute, Beihang University, China
5
days
Challenges in Cu PVD optimization for high-aspect-ratio via metallization
AuthorsHugo Nuez; Alice De Sousa Martins; Magali Gregoire; Rodolphe Bancheri; Julie Loche; Nassere Dine Hamdani
AffiliationsSTMicroelectronics, 850 Rue Jean Monnet, 38926 Crolles Cedex, France
2
days
Understanding the impact of vdW gap on the reliability of nanoscale MoS2 FETs by TCAD modeling
AuthorsYezhu Lv; Yehao Wu; Yury Yu. Illarionov
AffiliationsLaboratory of 2D Optoelectronics and Nanoelectronics (L2DON), State Key Laboratory of Quantum Functional Materials, Department of Materials Science and Engineering, Southern University of Science and Technology, Shenzhen, China
42
days
40 nm-thick Pt/(Al0.9Sc0.1)N/Pt ferroelectric capacitor stacks for logic-embedded memory on 300 mm Si with wafer-scale uniformity and process stability
AuthorsSoshun Doko; Naoko Matsui; Toshikazu Irisawa; Koji Tsunekawa; Kazuki Okamoto; Hiroshi Funakubo
AffiliationsCanon ANELVA Corporation, Kawasaki, Kanagawa 215-8550, Japan; Department of Material Science and Engineering, School of Materials and Chemical Technology, Institute of Science Tokyo, Yokohama, Kanagawa 226-8501, Japan; MDX Research Center for Element Strategy, International Research Frontiers Initiative, Institute of Science Tokyo, Yokohama, Kanagawa 226-8501, Japan
105
days
LWR-driven hot carrier degradation-induced variability in CMOS devices: mechanisms and mitigation
AuthorsYaoting Wang; Yongyu Wu; Hai Wang; Zenan Wang; Dawei Gao; Kai Xu
AffiliationsCollege of integrated circuits, Zhejiang University, Hangzhou, Zhejiang, CO 311200, China; Zhejiang ICsprout Semiconductor Company Ltd., Hangzhou 311200, China.; ZJU-Hangzhou Global Scientific and Technological Innovation Center, Hangzhou, Zhejiang, CO 311200, China; Zhejiang Technology Innovation Center of CMOS IC Manufacturing Process and Design, Hangzhou, Zhejiang, CO 311200, China
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SampleLatest 5 valid paper samples from 2026
Average review96.4 days
Median77 days