Paper Review Records
All Paper Review Records
20 valid samples · Newest publication first
Review days = acceptance date − received date. PDF, DOI, and publisher-page sources are retained.
72
days
The role of asymmetry in elevating nanosheet FET: RF and circuit metrics
AuthorsRaj Saha; Anubhab Saha; Akash Mandal; Tridib Kar; Subir Kumar Maity; Udai P. Singh; Rajendra Prasad
Affiliations1. School of Electronics Engineering, Kalinga Institute of Industrial Technology (KIIT) Deemed to be University, Bhubaneswar, India
88
days
Unveiling the impact of ITCs on High-k SOI GaN FinFET and its sensitivity analysis for improved reliability: a simulation study
AuthorsVandana Singh Rajawat; Bharat Choudhary; Ajay Kumar
Affiliations1. Department of Electronics & Communication Engineering, Malaviya National Institute of Technology, Jaipur, India; 2. Department of Electronics & Communication Engineering, Jaypee Institute of Information Technology, Noida, India
594
days
A 4.9 GS/s strongarm latch comparator topology with offset correction in 32-nm
AuthorsChokkakula Ganesh; A. Murali; B. Vamsy Krishna; T. Ananda Babu; Girraj Sharma; Asisa Kumar Panigrahy; M. Durga Prakash
Affiliations1. Deptartment of Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India; 2. Deptartment of Electronics and Communication Engineering, QIS College of Engineering and Technology, Ongole, Vengamukkapalem, India; 3. Department of Electronics and Communication Engineering, Seshadri Rao Gudlavalleru Engineering College, Andhra Pradesh, India; 4. Jindal Institute of Behavioural Sciences O.P. Jindal Global University, Sonipat, India; 5. Dept. of Electronics and Communication Engineering, Faculty of Science and Technology (IcfaiTech), ICFAI Foundation for Higher Education Hyderabad, Hyderabad, India; 6. Department of ECE, School of Engineering and Science, SRM University-AP, Mangalagiri, Andhra Pradesh, India
414
days
A self-correcting signal quantization based on error correcting codes
AuthorsGaël Mahé; Fatimetou El Jili; Mamadou Mboup
Affiliations1. LIPADE - URP 2517, Université Paris Cité, Paris, France; 2. CReSTIC - UR 3804, Université de Reims Champagne-Ardenne, Reims, France
195
days
A 0.439 \(ppm/^\circ{\rm C} \) CMOS bandgap reference with 4 \(\sim \) 40 V supply-range and high-order curvature compensations
AuthorsChunlai Wang; Shaobin Zhu; Yugeng Zhang; Muhammad Ahsan Farooq Qaisar; Weihua Han
Affiliations1. School of Physical Science and Technology, Lanzhou University, Lanzhou, China; 2. BASALT Semiconductor Co, Ltd, China
257
days
An FSK generator using CFOAs and electronically-controllable CMOS resistors
AuthorsManish Rai; A. K. Singh; Raj Senani
Affiliations1. Departement of Electrical, Electronics & Communication Engineering, Galgotias University, Plot-2, Sector-17A, Yamuna Expressway, Greater Noida, Gautan Budh Nagar, Uttar Pradesh, India; 2. Department of Electronics and Communication Engineering, Meerut Institute of Engineering and Technology, Meerut, India; 3. Departement of Electronics and Communication Engineering, NSUT, New Delhi, India; 4. Department of Electronics and Communication Engineering, Faculty of Technology, University of Delhi, Delhi, India
124
days
A comprehensive review of low-power design techniques in VLSI systems: From device physics to algorithmic optimization
AuthorsMarina Papadopoulou; Michael Dossis; Evangelos Karvounis
Affiliations1. Department of Computer Science, University of Western Macedonia, Kastoria, Greece
177
days
Low-Complexity VLSI architecture for OTFS transceiver under Fully Parallel and Pipelined Hardware Architecture using Cosine-Krawtchouk Point-wise Discrete Activations Tchebichef Steerable Lyrebird Convolutional Transforms Networks
AuthorsBalamurugan Rajangam; Maheswari Murali
Affiliations1. Department of Electronics and Communication Engineering, K.Ramakrishnan College of Engineering, Trichy, India
77
days
A scalable asynchronous Mod-10 BCD counter realization using delay flip-flops: A quantum-dot cellular automata approach
AuthorsRohit Kumar Shaw; Angshuman Khan; Sudip Halder
Affiliations1. Department of Electrical & Electronics Engineering, Birla Institute of Technology & Science (BITS) Pilani, Pilani, India; 2. Department of Electronics & Communication Engineering, University of Engineering & Management Jaipur, Jaipur, India; 3. Department of Electrical Engineering, K. E. Society’s Rajarambapu Institute of Technology Affiliated to Shivaji University Kolhapur, Islampur, India
143
days
A reconfigurable analog logic architecture based on clar cells for combinational and arithmetic systems
AuthorsJ. Gonzalez-Contreras; R. E. Lozoya-Ponce; L. J. Ontanon-Garcia
Affiliations1. División de Estudios de Posgrado e Investigación, I.T. Chihuahua - Tecnologico Nacional de Mexico, Chihuahua, México; 2. Coordinación Académica Región Altiplano Oeste, Universidad Autónoma de San Luis Potosí, Salinas de Hidalgo, México
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SampleLatest 5 valid paper samples from 2026
Average review96.4 days
Median77 days