Computer Science
Review Cycle Records
ACM Transactions on Reconfigurable Technology and Systems
Paper Review Records
All Paper Review Records
17 valid samples · Newest publication first
Review days = acceptance date − received date. PDF, DOI, and publisher-page sources are retained.
AIEAnalyzer: An Analytical Framework for Versal AI Engine Performance Analysis
AuthorsXinya Luan; Zhe Lin; Kai Shi; Liyang Dou; Jianwang Zhai; Kang Zhao
Affiliations1. Beijing University of Posts and Telecommunications, Beijing, China; 2. Sun Yat-Sen University, Shenzhen Campus, Guangzhou, China
A Perspective on the Topics from a Selection of Papers from the First 20 Years of the International Symposium on Applied Reconfigurable Computing (ARC)
AuthorsJoão M. P. Cardoso; Walid Najjar
Affiliations1. Faculty of Engineering, University of Porto, Porto, Portugal; 2. Computer Science and Engineering, University of California Riverside, Riverside, California, USA
HT-NoC: A Throughput-Adaptive Multi-Dataflow Network-on-Chip for AI Accelerators
AuthorsMohamed Amine Zhiri; Hana Krichene; Chiara Sandionigi; Sébastien Pillement
Affiliations1. Université Paris-Saclay, CEA, LIST, Palaiseau, France and Nantes Université, CNRS, IETR UMR 6164, Nantes, France; 2. Université Paris-Saclay, CEA, LIST, Palaiseau, France; 3. Université Grenoble Alpes, CEA, LIST, Grenoble, France; 4. Nantes Université, CNRS, IETR UMR 6164, Nantes, France
Fast SEU Detection and Recovery in FPGA-Based AI Accelerators
AuthorsGiorgio Cora; Eleonora Vacca; Corrado De Sio; Sarah Azimi; Luca Sterpone
Affiliations1. Department of Control and Computer Engineering, Politecnico di Torino, Turin, Italy
Streamlined Dataflow FPGA Architectures for Echo State Neural Networks in Time-Series Prediction and Classification Applications
AuthorsAtousa Jafari; Marco Platzner
Affiliations1. Paderborn University, Paderborn, Germany
An MLIR-Based Compilation Framework for Control Flow Management on Coarse-Grained Reconfigurable Arrays
AuthorsYuxuan Wang; Cristian Tirelli; Giovanni Ansaloni; Laura Pozzi; David Atienza
Affiliations1. ESL, EPFL, Lausanne, Switzerland; 2. University of Lugano (USI), Lugano, Switzerland
Hardware-Accelerated Graph Neural Networks: An Alternative Approach for Event-Based Audio Classification and Keyword Spotting on SoC FPGA
AuthorsKamil Jeziorek; Piotr Wzorek; Krzysztof Blachut; Hiroshi Nakano; Manon Dampfhoffer; Thomas Mesquida; Hiroaki Nishi; Thomas Dalgaty; Tomasz Kryjak
Affiliations1. Department of Automatic Control and Robotics, Embedded Perception and Autonomous Systems Group, AGH University of Krakow, Kraków, Poland; 2. Graduate School of Science and Technology, Keio University, Yokohama, Japan; 3. L’Université Grenoble Alpes, CEA, List, Grenoble, France
A 950 MHz SIMT Soft Processor
AuthorsMartin Langhammer; Gregg Baeckler; Kim Bozman
Affiliations1. Altera Corporation, London, United Kingdom of Great Britain and Northern Ireland; 2. Altera Corporation, San Jose, California, USA; 3. Altera Corporation, Toronto, Ontario, Canada
A Configurable RISC-V Co-Processor with Instruction-Controlled Stream-Based Accelerators
AuthorsRohan Krishna Vijayaraghavan; Ahmed Kamaleldin; Matthias Nickel; Lester Kalms; Diana Göhringer
Affiliations1. TU Dresden, Chair of Adaptive Dynamic Systems, Dresden, Germany
BitBlender: Scalable, High-Throughput Bloom Filter Acceleration on FPGAs with Dynamic Scheduling
AuthorsKenneth Liu; Zhenman Fang
Affiliations1. School of Engineering Science, Simon Fraser University, Burnaby, British Columbia, Canada; 2. School of Engineering Science, Simon Fraser University, Burnaby, British Columbia, Canada and Electrical and Computer Engineering, University of Minnesota Twin Cities, Minneapolis, Minnesota, USA
Expert Matching · Case Demo
Turn Your Submission Goalsinto a Verifiable Journal Plan
Share your field, deadline, and author profile. CrushSCI uses real review records to suggest a title direction, shortlist journals, and estimate timelines.