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Review Cycle Records

ACM Transactions on Reconfigurable Technology and Systems

ACM SCIE 非OA

2026新锐 3区2025中科院 3区2025 JCR Q2

查看审稿周期计算与数据来源报告数据问题

224.2平均天数

206中位天数

147最短天数

367最长天数

492025发文量

Paper Review Records

全部论文审稿周期

17 篇有效样本 · 按发表日期由新到旧排列
审稿天数=录用日期-收稿日期；保留 PDF/DOI/网页源链接

170 天

AIEAnalyzer: An Analytical Framework for Versal AI Engine Performance Analysis

收稿 2025-10-21 录用 2026-04-09 发表 2026-09-08

作者Xinya Luan; Zhe Lin; Kai Shi; Liyang Dou; Jianwang Zhai; Kang Zhao

作者单位1. Beijing University of Posts and Telecommunications, Beijing, China; 2. Sun Yat-Sen University, Shenzhen Campus, Guangzhou, China

PDF源文件 DOI 网页

182 天

A Perspective on the Topics from a Selection of Papers from the First 20 Years of the International Symposium on Applied Reconfigurable Computing (ARC)

收稿 2025-12-09 录用 2026-06-09 发表 2026-09-08

作者João M. P. Cardoso; Walid Najjar

作者单位1. Faculty of Engineering, University of Porto, Porto, Portugal; 2. Computer Science and Engineering, University of California Riverside, Riverside, California, USA

PDF源文件 DOI 网页

199 天

HT-NoC: A Throughput-Adaptive Multi-Dataflow Network-on-Chip for AI Accelerators

收稿 2025-08-30 录用 2026-03-17 发表 2026-09-08

作者Mohamed Amine Zhiri; Hana Krichene; Chiara Sandionigi; Sébastien Pillement

作者单位1. Université Paris-Saclay, CEA, LIST, Palaiseau, France and Nantes Université, CNRS, IETR UMR 6164, Nantes, France; 2. Université Paris-Saclay, CEA, LIST, Palaiseau, France; 3. Université Grenoble Alpes, CEA, LIST, Grenoble, France; 4. Nantes Université, CNRS, IETR UMR 6164, Nantes, France

PDF源文件 DOI 网页

206 天

Fast SEU Detection and Recovery in FPGA-Based AI Accelerators

收稿 2025-08-28 录用 2026-03-22 发表 2026-09-08

作者Giorgio Cora; Eleonora Vacca; Corrado De Sio; Sarah Azimi; Luca Sterpone

作者单位1. Department of Control and Computer Engineering, Politecnico di Torino, Turin, Italy

PDF源文件 DOI 网页

211 天

Streamlined Dataflow FPGA Architectures for Echo State Neural Networks in Time-Series Prediction and Classification Applications

收稿 2025-09-02 录用 2026-04-01 发表 2026-09-08

作者Atousa Jafari; Marco Platzner

作者单位1. Paderborn University, Paderborn, Germany

PDF源文件 DOI 网页

300 天

An MLIR-Based Compilation Framework for Control Flow Management on Coarse-Grained Reconfigurable Arrays

收稿 2025-08-19 录用 2026-06-15 发表 2026-09-08

作者Yuxuan Wang; Cristian Tirelli; Giovanni Ansaloni; Laura Pozzi; David Atienza

作者单位1. ESL, EPFL, Lausanne, Switzerland; 2. University of Lugano (USI), Lugano, Switzerland

PDF源文件 DOI 网页

315 天

Hardware-Accelerated Graph Neural Networks: An Alternative Approach for Event-Based Audio Classification and Keyword Spotting on SoC FPGA

收稿 2025-09-13 录用 2026-07-25 发表 2026-09-08

作者Kamil Jeziorek; Piotr Wzorek; Krzysztof Blachut; Hiroshi Nakano; Manon Dampfhoffer; Thomas Mesquida; Hiroaki Nishi; Thomas Dalgaty; Tomasz Kryjak

作者单位1. Department of Automatic Control and Robotics, Embedded Perception and Autonomous Systems Group, AGH University of Krakow, Kraków, Poland; 2. Graduate School of Science and Technology, Keio University, Yokohama, Japan; 3. L’Université Grenoble Alpes, CEA, List, Grenoble, France

PDF源文件 DOI 网页

190 天

A 950 MHz SIMT Soft Processor

收稿 2025-09-23 录用 2026-04-01 发表 2026-08-12

作者Martin Langhammer; Gregg Baeckler; Kim Bozman

作者单位1. Altera Corporation, London, United Kingdom of Great Britain and Northern Ireland; 2. Altera Corporation, San Jose, California, USA; 3. Altera Corporation, Toronto, Ontario, Canada

PDF源文件 DOI 网页

207 天

A Configurable RISC-V Co-Processor with Instruction-Controlled Stream-Based Accelerators

收稿 2025-10-01 录用 2026-04-26 发表 2026-08-12

作者Rohan Krishna Vijayaraghavan; Ahmed Kamaleldin; Matthias Nickel; Lester Kalms; Diana Göhringer

作者单位1. TU Dresden, Chair of Adaptive Dynamic Systems, Dresden, Germany

PDF源文件 DOI 网页

367 天

BitBlender: Scalable, High-Throughput Bloom Filter Acceleration on FPGAs with Dynamic Scheduling

收稿 2025-04-24 录用 2026-04-26 发表 2026-08-12

作者Kenneth Liu; Zhenman Fang

作者单位1. School of Engineering Science, Simon Fraser University, Burnaby, British Columbia, Canada; 2. School of Engineering Science, Simon Fraser University, Burnaby, British Columbia, Canada and Electrical and Computer Engineering, University of Minnesota Twin Cities, Minneapolis, Minnesota, USA

PDF源文件 DOI 网页

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拟题建议: 《融合机器学习与生命周期评价的城市污水处理碳排放预测与优化》
数据库初筛: Environmental Technology & Innovation

样本口径2026 年最近 5 篇有效论文样本

平均审稿96.4 天

中位数77 天

ACM Transactions on Reconfigurable Technology and Systems

全部论文审稿周期

AIEAnalyzer: An Analytical Framework for Versal AI Engine Performance Analysis

A Perspective on the Topics from a Selection of Papers from the First 20 Years of the International Symposium on Applied Reconfigurable Computing (ARC)

HT-NoC: A Throughput-Adaptive Multi-Dataflow Network-on-Chip for AI Accelerators

Fast SEU Detection and Recovery in FPGA-Based AI Accelerators

Streamlined Dataflow FPGA Architectures for Echo State Neural Networks in Time-Series Prediction and Classification Applications

An MLIR-Based Compilation Framework for Control Flow Management on Coarse-Grained Reconfigurable Arrays

Hardware-Accelerated Graph Neural Networks: An Alternative Approach for Event-Based Audio Classification and Keyword Spotting on SoC FPGA

A 950 MHz SIMT Soft Processor

A Configurable RISC-V Co-Processor with Instruction-Controlled Stream-Based Accelerators

BitBlender: Scalable, High-Throughput Bloom Filter Acceleration on FPGAs with Dynamic Scheduling

把投稿要求，转成可验证的期刊方案

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ACM Transactions on Reconfigurable Technology and Systems

全部论文审稿周期

AIEAnalyzer: An Analytical Framework for Versal AI Engine Performance Analysis

A Perspective on the Topics from a Selection of Papers from the First 20 Years of the International Symposium on Applied Reconfigurable Computing (ARC)

HT-NoC: A Throughput-Adaptive Multi-Dataflow Network-on-Chip for AI Accelerators

Fast SEU Detection and Recovery in FPGA-Based AI Accelerators

Streamlined Dataflow FPGA Architectures for Echo State Neural Networks in Time-Series Prediction and Classification Applications

An MLIR-Based Compilation Framework for Control Flow Management on Coarse-Grained Reconfigurable Arrays

Hardware-Accelerated Graph Neural Networks: An Alternative Approach for Event-Based Audio Classification and Keyword Spotting on SoC FPGA

A 950 MHz SIMT Soft Processor

A Configurable RISC-V Co-Processor with Instruction-Controlled Stream-Based Accelerators

BitBlender: Scalable, High-Throughput Bloom Filter Acceleration on FPGAs with Dynamic Scheduling

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