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全部论文审稿周期

25 篇有效样本 · 按发表日期由新到旧排列
审稿天数=录用日期-收稿日期;保留 PDF/DOI/网页源链接

414 天

A self-correcting signal quantization based on error correcting codes

作者
Gaël Mahé; Fatimetou El Jili; Mamadou Mboup展开收起
作者单位
1. LIPADE - URP 2517, Université Paris Cité, Paris, France; 2. CReSTIC - UR 3804, Université de Reims Champagne-Ardenne, Reims, France展开收起
PDF源文件 DOI 网页
195 天

A 0.439 \(ppm/^\circ{\rm C} \) CMOS bandgap reference with 4 \(\sim \) 40 V supply-range and high-order curvature compensations

作者
Chunlai Wang; Shaobin Zhu; Yugeng Zhang; Muhammad Ahsan Farooq Qaisar; Weihua Han展开收起
作者单位
1. School of Physical Science and Technology, Lanzhou University, Lanzhou, China; 2. BASALT Semiconductor Co, Ltd, China展开收起
PDF源文件 DOI 网页
257 天

An FSK generator using CFOAs and electronically-controllable CMOS resistors

作者
Manish Rai; A. K. Singh; Raj Senani展开收起
作者单位
1. Departement of Electrical, Electronics & Communication Engineering, Galgotias University, Plot-2, Sector-17A, Yamuna Expressway, Greater Noida, Gautan Budh Nagar, Uttar Pradesh, India; 2. Department of Electronics and Communication Engineering, Meerut Institute of Engineering and Technology, Meerut, India; 3. Departement of Electronics and Communication Engineering, NSUT, New Delhi, India; 4. Department of Electronics and Communication Engineering, Faculty of Technology, University of Delhi, Delhi, India展开收起
PDF源文件 DOI 网页
124 天

A comprehensive review of low-power design techniques in VLSI systems: From device physics to algorithmic optimization

作者
Marina Papadopoulou; Michael Dossis; Evangelos Karvounis展开收起
作者单位
1. Department of Computer Science, University of Western Macedonia, Kastoria, Greece展开收起
PDF源文件 DOI 网页
177 天

Low-Complexity VLSI architecture for OTFS transceiver under Fully Parallel and Pipelined Hardware Architecture using Cosine-Krawtchouk Point-wise Discrete Activations Tchebichef Steerable Lyrebird Convolutional Transforms Networks

作者
Balamurugan Rajangam; Maheswari Murali展开收起
作者单位
1. Department of Electronics and Communication Engineering, K.Ramakrishnan College of Engineering, Trichy, India展开收起
PDF源文件 DOI 网页
77 天

A scalable asynchronous Mod-10 BCD counter realization using delay flip-flops: A quantum-dot cellular automata approach

作者
Rohit Kumar Shaw; Angshuman Khan; Sudip Halder展开收起
作者单位
1. Department of Electrical & Electronics Engineering, Birla Institute of Technology & Science (BITS) Pilani, Pilani, India; 2. Department of Electronics & Communication Engineering, University of Engineering & Management Jaipur, Jaipur, India; 3. Department of Electrical Engineering, K. E. Society’s Rajarambapu Institute of Technology Affiliated to Shivaji University Kolhapur, Islampur, India展开收起
PDF源文件 DOI 网页

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样本口径2026 年最近 5 篇有效论文样本

平均审稿62 天

中位数65 天

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