期刊审稿周期图谱
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 期刊封面
← 返回期刊列表

Review Cycle Records

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING

Springer 非OA 2026新锐 4区2025中科院 4区 已自动采集 最新完整样本 10 篇 平均 214.1 天

数据更新 2026-07-15 · 完整周期 10 篇 · 日期来源可逐条复核

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING已收录10篇完整论文周期样本,平均审稿214.1 天,中位审稿160 天。2025中科院4区,非OA,2025发文量245。页面含论文收到日期、录用日期、PDF、DOI和出版社网页溯源入口。

214.1平均天数
160中位天数
72最短天数
594最长天数
10最新论文
2452025发文量

Latest Papers

最新发表论文审稿周期

审稿天数=录用日期-收到日期;保留 PDF/DOI/网页源链接

72

The role of asymmetry in elevating nanosheet FET: RF and circuit metrics

作者Raj Saha; Anubhab Saha; Akash Mandal; Tridib Kar; Subir Kumar Maity; Udai P. Singh; Rajendra Prasad

作者单位1. School of Electronics Engineering, Kalinga Institute of Industrial Technology (KIIT) Deemed to be University, Bhubaneswar, India

PDF源文件 DOI 网页
88

Unveiling the impact of ITCs on High-k SOI GaN FinFET and its sensitivity analysis for improved reliability: a simulation study

作者Vandana Singh Rajawat; Bharat Choudhary; Ajay Kumar

作者单位1. Department of Electronics & Communication Engineering, Malaviya National Institute of Technology, Jaipur, India; 2. Department of Electronics & Communication Engineering, Jaypee Institute of Information Technology, Noida, India

PDF源文件 DOI 网页
594

A 4.9 GS/s strongarm latch comparator topology with offset correction in 32-nm

作者Chokkakula Ganesh; A. Murali; B. Vamsy Krishna; T. Ananda Babu; Girraj Sharma; Asisa Kumar Panigrahy; M. Durga Prakash

作者单位1. Deptartment of Electronics and Communication Engineering, VNR Vignana Jyothi Institute of Engineering and Technology, Hyderabad, India; 2. Deptartment of Electronics and Communication Engineering, QIS College of Engineering and Technology, Ongole, Vengamukkapalem, India; 3. Department of Electronics and Communication Engineering, Seshadri Rao Gudlavalleru Engineering College, Andhra Pradesh, India; 4. Jindal Institute of Behavioural Sciences O.P. Jindal Global University, Sonipat, India; 5. Dept. of Electronics and Communication Engineering, Faculty of Science and Technology (IcfaiTech), ICFAI Foundation for Higher Education Hyderabad, Hyderabad, India; 6. Department of ECE, School of Engineering and Science, SRM University-AP, Mangalagiri, Andhra Pradesh, India

PDF源文件 DOI 网页
414

A self-correcting signal quantization based on error correcting codes

作者Gaël Mahé; Fatimetou El Jili; Mamadou Mboup

作者单位1. LIPADE - URP 2517, Université Paris Cité, Paris, France; 2. CReSTIC - UR 3804, Université de Reims Champagne-Ardenne, Reims, France

PDF源文件 DOI 网页
195

A 0.439 \(ppm/^\circ{\rm C} \) CMOS bandgap reference with 4 \(\sim \) 40 V supply-range and high-order curvature compensations

作者Chunlai Wang; Shaobin Zhu; Yugeng Zhang; Muhammad Ahsan Farooq Qaisar; Weihua Han

作者单位1. School of Physical Science and Technology, Lanzhou University, Lanzhou, China; 2. BASALT Semiconductor Co, Ltd, China

PDF源文件 DOI 网页
257

An FSK generator using CFOAs and electronically-controllable CMOS resistors

作者Manish Rai; A. K. Singh; Raj Senani

作者单位1. Departement of Electrical, Electronics & Communication Engineering, Galgotias University, Plot-2, Sector-17A, Yamuna Expressway, Greater Noida, Gautan Budh Nagar, Uttar Pradesh, India; 2. Department of Electronics and Communication Engineering, Meerut Institute of Engineering and Technology, Meerut, India; 3. Departement of Electronics and Communication Engineering, NSUT, New Delhi, India; 4. Department of Electronics and Communication Engineering, Faculty of Technology, University of Delhi, Delhi, India

PDF源文件 DOI 网页
124

A comprehensive review of low-power design techniques in VLSI systems: From device physics to algorithmic optimization

作者Marina Papadopoulou; Michael Dossis; Evangelos Karvounis

作者单位1. Department of Computer Science, University of Western Macedonia, Kastoria, Greece

PDF源文件 DOI 网页
177

Low-Complexity VLSI architecture for OTFS transceiver under Fully Parallel and Pipelined Hardware Architecture using Cosine-Krawtchouk Point-wise Discrete Activations Tchebichef Steerable Lyrebird Convolutional Transforms Networks

作者Balamurugan Rajangam; Maheswari Murali

作者单位1. Department of Electronics and Communication Engineering, K.Ramakrishnan College of Engineering, Trichy, India

PDF源文件 DOI 网页
77

A scalable asynchronous Mod-10 BCD counter realization using delay flip-flops: A quantum-dot cellular automata approach

作者Rohit Kumar Shaw; Angshuman Khan; Sudip Halder

作者单位1. Department of Electrical & Electronics Engineering, Birla Institute of Technology & Science (BITS) Pilani, Pilani, India; 2. Department of Electronics & Communication Engineering, University of Engineering & Management Jaipur, Jaipur, India; 3. Department of Electrical Engineering, K. E. Society’s Rajarambapu Institute of Technology Affiliated to Shivaji University Kolhapur, Islampur, India

PDF源文件 DOI 网页
143

A reconfigurable analog logic architecture based on clar cells for combinational and arithmetic systems

作者J. Gonzalez-Contreras; R. E. Lozoya-Ponce; L. J. Ontanon-Garcia

作者单位1. División de Estudios de Posgrado e Investigación, I.T. Chihuahua - Tecnologico Nacional de Mexico, Chihuahua, México; 2. Coordinación Académica Región Altiplano Oeste, Universidad Autónoma de San Luis Potosí, Salinas de Hidalgo, México

PDF源文件 DOI 网页